This invention concerns a random access memory for digital data, particularly a memory having a data output rate substantially higher than the rate at which data can be accessed in the memory.
Random access memories (RAMs) have been used for years in digital systems to store digital data. Conventionally, RAMs consist of not only memory circuitry but also input and output circuitry all on a single chip of semiconductor material which is contained in a single integrated circuit packaged on a 16 pin base. As their technology has progressed, a variety of different RAMs have been developed including those with provisions for non-destructive reading of stored digital information, those in which the stored digital information is non-volatile and need not be refreshed periodically, those incorporating their own internal address decoding circuits, those incorporating relatively high-speed bipolar logic elements, and those incorporating relatively slower, metal oxide semiconductor (MOS) elements. While such MOS RAMs are much cheaper than bipolar RAMs, because they require significantly longer times to access stored data, their use is becoming more and more limited as digital systems improve to the point where memory access time determines their operating speed.
Accordingly, a major object of this invention is to provide a high-speed data output system for a low-speed random access memory, particularly a MOS RAM. Other objects of this invention will be apparent to those skilled in the art from the following detailed description of a preferred embodiment.